In recent years, researchers have explored use of non-volatile devices suchas STT-RAM (spin torque transfer RAM) for designing on-chip caches, since theyprovide high density and consume low leakage power. A common limitation of allnon-volatile devices is their limited write endurance. Further, since existingcache management policies are write-variation unaware, excessive writes to afew blocks may lead to a quick failure of the whole cache. We propose anarchitectural technique for wear-leveling of non-volatile last level caches(LLCs). Our technique uses cache-coloring approach which adds asoftware-controlled mapping layer between groups of physical pages and cachesets. Periodically the mapping is altered to ensure that write-traffic can bespread uniformly to different sets of the cache to achieve wear-leveling.Simulations performed with an x86-64 simulator and SPEC2006 benchmarks showthat our technique reduces the worst-case writes to cache blocks and thusimproves the cache lifetime by 4.07X.
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